1. Field of the Invention
The present invention relates to a negative reference voltage generating circuit used in, for example, a NOR-type flash memory to generate a negative reference voltage, and a negative reference voltage generating system using the same.
2. Description of the Related Art
FIGS. 6A and 6B are cross section views of a NOR-type flash memory according to Conventional Example 1. FIGS. 6A and 6B respectively show necessary voltages for performing programming/erasing operations by Fowler-Nordheim tunneling with the maximum voltages 18V and 10V. In FIGS. 6A and 6B, 100 is a semiconductor substrate, 101 is a control gate, 102 is a source, 103 is a drain, and 104 is a floating gate.
For example, an NOR type flash memory needs high-speed performance on random access. As shown in FIGS. 6A and 6B, a positive middle voltage such as 10V and a negative middle voltage such as −8V are adopted to substitute for a positive high voltage to perform programming/erasing operations. By using the positive middle voltage and negative middle voltage, MOS transistors in peripheral circuits show higher performance than high-voltage transistors. The reason is that a thin gate oxide film and a short gate length can be used.
To generate positive voltages, a bandgap reference voltage generating circuit is often used, for example, in the peripheral circuits of an NAND type flash memory.
The prior art documents are listed as follows:    Patent document 1: US 2012-0218032    Patent document 2: JP 2009-016929    Patent document 3: JP 2009-074973    Patent document 4: US 2008-0018318    Patent document 5: JP H10-239357    Patent document 6: JP 2000-339047    Patent document 7: JP 2002-367374    Patent document 8: US 2012-155168    Patent document 9: WO 2006-025099    Patent document 10: JP 2004-350290    Non-patent document 1: Comel Stanescu et al., “High PSRR CMOS Voltage Reference for Negative IDOS”, Proceedings of 2004 International Semiconductor Conference (CAS 2004), 27th Edition, Oct. 4-6, 2004, in Sinaia, Romania.    Non-patent document 2: Oguey et al., “MOS Voltage Reference Based on Polysilicon Gate Work Function Difference”, IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 3, June 1980.
However, to generate negative voltages, the bandgap reference voltage generating circuit for generating negative voltages as described above is not usually used. It is common for the bandgap reference voltage generating circuits of positive voltage to be used to generate a negative reference voltage as shown in FIGS. 7 and 8.
FIG. 7 is a circuit diagram showing a negative voltage generator 2 disclosed in Patent document 1 according to Conventional Example 2. In FIG. 7, the negative voltage generator 2 is composed of resistors R21, R22, a differential amplifier 20, and a charge pump 21. Here, Vdd is a positive supply voltage, Vss is a ground voltage, and the positive supply voltage Vpp applied to the resistor R1 is regulated according to the positive reference voltage PVref. The negative voltage Vneg which is generated by the negative voltage generator 2 of FIG. 7 is obtained from the following equation:Vneg=−R22/R21×Vpp+(1+R22/R21)×PVref  (1)
FIG. 8 is a circuit diagram showing a negative voltage generating circuit disclosed in Patent documents 2 and 3 according to Conventional Example 3. In FIG. 8, the negative voltage generating circuit is composed of differential amplifier 31 and 32, p-channel MOS transistors (called PMOS transistors in the following description) P31 and P32, resistors R31 and R32, and a charge pump 33. Here, Vdd is a positive supply voltage, Vss is a ground voltage. The PMOS transistors P31 and P32 compose a current mirror and make the same reference current flow through the resistors R31 and R32. The negative voltage Vneg which is generated by the negative voltage generating circuit of FIG. 8 is shown as the following equation:Vneg=−Iref×R32+PVref  (2)Iref=PVref/R31  (3)
However, if a negative reference voltage NVref can be used, a more precise negative voltage Vneg can be generated and the circuit structure can be simple. To generate a negative voltage Vneg=−10V, if the negative reference voltage NVref=−1.0V+0.1V, the negative voltage Vneg will be controlled at −10V+1V which has an error tenfold that of the negative reference voltage NVref. Therefore, the negative voltage generating circuit needs an accuracy of ±0.01V, the same as the bandgap reference generating circuit.
FIG. 9 is a circuit diagram showing a negative voltage generating circuit according to this concept, the structure of which is the same as a positive voltage generating circuit which uses a positive reference voltage. The negative voltage generating circuit of FIG. 9 is composed of resistors R41 and R42, a differential amplifier 41, and a charge pump 42. In FIG. 9, the resistors R41 and R42 which compose a voltage divider circuit can be replaced by a series circuit of two capacitors. Here, The negative voltage Vneg which is generated from the negative voltage generating circuit of FIG. 9 is shown as the following equation:Vneg=(R42/R41+1)×NVref  (4)
The problem is how to realize a circuit which accurately generates the negative reference voltage NVref. FIG. 10 is a circuit diagram showing a negative reference voltage generating circuit according to Conventional Example 4. The negative reference voltage generating circuit of FIG. 10 is composed of a current source 50 which generates reference current Iref according to the positive reference voltage PVref, resistors R51 and R52, and n-channel MOS transistors (called NMOS transistors in the following description) N51 and N52. The negative reference voltage NVref which is generated by the negative reference voltage generating circuit of FIG. 10 is shown as the following equation:NVref=Iref×R52  (5)
FIG. 11 is a circuit diagram showing a negative reference voltage generating circuit according to Conventional Example 5. The negative reference voltage generating circuit of FIG. 11 is composed of resistors R61 and R62, and a differential amplifier 60. The negative reference voltage NVref which is generated by the negative reference voltage generating circuit of FIG. 11 is shown as the following equation:NVref=−PVref×R62/R61  (6)
Regarding the control circuits of Conventional Examples, the negative reference voltage is obtained from the positive reference voltage, and this can cause some errors in addition to an inaccuracy of the positive reference voltage PVref. The control circuits of Conventional Examples are classified as two types.
(Type 1 (FIG. 10)) A reference current Iref is generated from the positive reference voltage PVref, and the negative reference voltage NVref is generated by the equation Iref×R according to the reference current Iref (for example, Patent document 4). In this case, the operation conditions are not exactly the same because a current mirror is used. Therefore, there are more errors involved. Moreover, there is an unnecessary offset of the differential amplifier involved.
(Type 2 (FIG. 11)) Using the comparator circuit between the negative reference voltage NVref and the positive reference voltage PVref, the negative reference voltage NVref is generated by inverting the positive reference circuit PVref generated as antenna power. In this case, the positive reference voltage PVref is used as the power source, leading to errors due to generation of the positive reference voltage PVref for the power source and errors of its voltage-drop due to the fact that current is being drawn.
Further, in Patent document 10, in order to provide a bandgap reference voltage generator which doesn't need a trimming circuit, a reference voltage generator unit is used. However, a heat-sensing circuit using diadodes is necessary to realize the reference voltage generator unit, and this makes the circuit structure more complicated. Note that the bandgap reference voltage generator is, for example, a positive reference voltage generator of 1.25V, but not a circuit for generating negative reference voltage.
In order to solve the above problems, the invention provides a negative reference voltage generating circuit and a negative reference voltage generating system which can more accurately generate a negative reference voltage and have a simple circuit structure compared to the prior art.